Relocation Hardware

• Relocation Registers: Relative address (bin) + Starting address (dynamic) = Real address (2 new registers: base & limit, updated in context switch)

Paging

1. Page Frames: Partition physical memory into equal chunks (e.g. 4kb)
2. Virtual Pages (page): Divide the process’ memory into the same chunks
3. Any page can be assigned to any free frame
   • Eliminate external fragmentation, and internal fragmentation at most one page per region

• Virtual pages can be swapped to disk
• Address translation has an overhead

Page Table: Store VA (virtual addr) to PA (physical addr) page lookup table per proc

• Required hardware: pbtr page table base register

  pg = VA / psize  # Top n bits (= VA >> n)
  offset = VA % psize  # Bottom n bits (n = 12 bits for 4kb)
  frame = page_table[pg]
  PA = frame * psize + offset
  

Page Table Entry (PET) ⭐️

• [ Flags (MRV) 3 bits ][ Prot (RWX) 3 bits ][ Page Frame Number 26 bits ]
• M - Modified Bit: If the page is written (dirty)
• R - Referenced Bit: If the page is read
• V - Valid Bit: If this PTE is used
• Prot RWX: Permission control for read/write/exec (prevent stack execution)
• PFN: Physical frame address

Page Table Design

Problem: Page tables take up a lot of space ($2^{20}\cdot 4k=4M$ for each process)

Dynamic Paging: Grow page table as needed

• Doesn’t work since the code segment is at the bottom and stack is at top of VA

Segmented Paging: Each segment has their own page tables

• Limited number of regions (segments)
• Still have page table waste for e.g. sparse heap
• Cause external fragmentation

Two-Level Hierarchical Page Table: Split page into page directory PDI and page table index PTI

• Page directory point to the base of the secondary page table

64-Bit Virtual Address: 48 bits used, 4 level page tables (9 bits each)