Memory

Bistable Element

Bistable Element: A circuit element that stores 2 stable states (0 and 1)

SR Latch

• When $S,R$ are 0, $Q,\bar Q$ retains their previous state
• When $S$ is 1, $Q$ is set to 1, $\bar Q =0$
• When $R$ is 1, $Q$ is reset to 0, $\bar Q =1$
• When both $S,R$ are 1, $Q=\bar Q =0$ (stupid)

D Latch

• Two inputs: $D$ is the value that should be stored, $CLK$ turns on when $Q$ should update

• Latch is transparent when CLK=1

• Latch is opaque when CLK=0

• Downside: Q will always update when CLK=1 (When chaining D-latches, all Qs will switch when CLK=1)

D Flip-Flop

• Copies D to Q on the rising edge, retains state at other times
• Aka. Master-Slave Flip-Flip / Edge-Triggered Flip-Flip
• On test: Say “Assume Q is initially 0”

Clock Signal

Clock: Pulse of a digital system, change between 0 and 1

• Rising Clock Edge: Transition from 0 to 1
• Period: Time between rising edges of the clock
• Frequency: Inverse of period

Synchronous Sequential Circuits

Synchronous Sequential Circuit: Comb circuit + at least 1 register (N-bit D Flip-Flop)

• All registers receive the same clock signal
• Every cyclic path contain at least one register

Timing Constraints

• Setup Time: $t_{setup}$ Input to a register must be stable for some time before the clock edge