RISC Design Philosophy

  1. Simplicity favors regularity (Every instruction is 32-bit with 6-bit opcode)
  2. Make the common case fast (Include commonly used instructions)
  3. Smaller is faster (Size of register impacts speed)
  4. Good design demands good compromises (Even though adding complexity, we have multiple instruction types)

Machine Instructions

R-Type Instructions (e.g. add, addu, div, mult, sub)

op rs rt rd shamt funct
6bit, 000000 u5, register u5, register u5, register 5bit 6bit, operation

I-Type Instructions (e.g. addi, addiu)

op rs rt imm
6bit, operation u5, register u5, register 16bit, constant value

J-Type Instructions

op addr
6bit, operation u26, address

Pseudo Instructions: Instructions added by the assembler

Assembly Code

add $s0, $s1, $s2
sub $t0, $t3, $t5

Machine Code

op rs rt rd shamt funct
0 17 18 16 0 100000
0 11 13 8 0 100010

Memory Operation: Load & Store

Load Word lw <reg dest> <mem src (base + offset)>: Load from memory to register

Store Word sw <reg src> <mem dest>: Store from register to memory